ROV=Val_0x0, RBALL=Val_0x0, SACK=Val_0x0, RSTAT=Val_0x0, ROM=Val_0x0, RREL=Val_0x0
Receive Control Register
| RSTAT | Receive Buffer Status. 0 (Val_0x0): Empty 1 (Val_0x1): > Empty and < almost full (CANFD_LIMIT[AFWL]) 2 (Val_0x2): Almost full (programmable threshold by the CANFD_LIMIT[AFWL] bit field) but not full and no overflow 3 (Val_0x3): Full (stays set in case of overflow-for overflow signaling, see the ROV bit) |
| RBALL | Receive Buffer Stores All Data Frames. 0 (Val_0x0): Normal operation 1 (Val_0x1): RB stores correct data frames as well as data frames with error (refer to Section Reception of All Data Frames (CANFD_RCTRL[RBALL])) |
| RREL | Receive Buffer Release. The host controller has read the actual RB slot and releases it. Afterwards the CAN controller points to the next RB slot. The RSTAT bit field gets updated. 0 (Val_0x0): No release 1 (Val_0x1): Release: The host has read the RB |
| ROV | Receive Buffer Overflow. This bit is cleared by setting the RREL = 0x1. 0 (Val_0x0): No Overflow 1 (Val_0x1): Overflow. At least one message is lost |
| ROM | Receive Buffer Overflow Mode. In case of a full RBUF when a new message is received, then this bit selects the following: 0 (Val_0x0): The oldest message will be overwritten 1 (Val_0x1): The new message will not be stored |
| SACK | Self-Acknowledge. 0 (Val_0x0): No self-ACK 1 (Val_0x1): Self-ACK when the CANFD_CFG_STAT[LBME] = 0x1 |